Perf/batch byte range checks#487
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reducing interactions from 68 to 56
Codex Code Review
No other significant security/bug/performance issues stood out in the diff. |
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Benchmark — fib_iterative_8M (median of 3)Table parallelism: 32 (auto = cores / 3)
Commit: 18b8424 · Baseline: cached · Runner: self-hosted bench |
Review summaryOne security concern (inline) and two stale comments. Stale comments not updated by this PR
The main security concern is filed as an inline comment on line 515 (the incorrect claim that IS_HALF implies per-byte range). These two lines were not in the diff so couldn't be filed inline. |
bus values for individual byte verification
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Codex Code Review
No other concrete security/correctness/performance issues stood out in the diffed changes. Test gap: I could not run cargo tests in this environment because |
ReviewSoundness: previous "Critical" concern was a false positiveBoth the first Codex comment and the previous Claude inline were based on a misread of the approach. The concern was about IS_HALF-style packing ( The PR sends X and Y as two independent Medium — BusId renumbering is a silent protocol break
Low — PR description off-by-oneThe description says "reducing CPU bus interactions from 68 to 56 (-18%)" but the math and the test both give 55: 27 IS_BYTE → 14 IS_BYTE = −13 interactions; 68 − 13 = 55. The test in |
Code reviewNo issues found. Checked for bugs and CLAUDE.md compliance. Reviewed: byte pairing logic correctness, BusId renumbering consistency, bus interaction value counts, soundness of dual-byte IS_BYTE[X, Y] lookups, trace builder padding alignment, and PAGE/BRANCH single-byte (Y=0) convention. 🤖 Generated with Claude Code - If this code review was useful, please react with 👍. Otherwise, react with 👎. |
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Review: Perf/batch byte range checks Overall: The batching optimization is sound. Pairing two byte columns into one IS_BYTE[X,Y] lookup is safe because the BITWISE table contains rows for every (x,y) in [0,255]x[0,255], so both values are individually constrained. The count drop from 68 to 55 CPU bus interactions checks out (27 IS_BYTE to 14 = 13 fewer). Medium - Unexplained BusId gap at value 2 (see inline comment on types.rs) IsB20 is explicitly pinned to = 3, but nothing is inserted at position 2. This makes TryFrom(2) return Err(2) where it previously returned IsB20, and shifts every channel ID from IsB20 onward by +1 (AndByte 3->4, Commit 21->22) - a protocol-breaking change for stored proof artifacts. If slot 2 is intentionally reserved, document it. If unintentional, drop the = 3 so the numbering stays contiguous. Low - PR description says 56 interactions, code says 55 The description states reducing CPU bus interactions from 68 to 56 (-18%) but cpu_tests.rs asserts interactions.len() == 55 (68 - 13 = 55). Minor doc discrepancy. |
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Code reviewNo issues found. Checked for bugs and CLAUDE.md compliance. Notes (below threshold, informational only):
🤖 Generated with Claude Code - If this code review was useful, please react with 👍. Otherwise, react with 👎. |
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Review: Perf/batch byte range checks The optimization is cryptographically sound. The BITWISE table already enumerates all 65536 (X, Y) byte pairs for AND/OR/XOR, so re-using those rows for IS_BYTE[X, Y] is valid - the LogUp fingerprint includes both values, so an out-of-range byte in either position has no matching table row and the proof fails. Multiplicity accounting looks consistent between bus_interactions(), collect_byte_check_ops(), and the padding helper (all produce 14 ops per CPU row: 1+1+12). Issues: Medium - Pre-existing test bug fixed here (inline on prove_elfs_tests.rs:1007): bus_id = 17 was BusId::Branch, not BusId::Memory (which is 16 in the enum). Good catch. Suggest using the named constant directly to prevent future drift. Low - PR description says "68 to 56 (-18%)" but the assertion and its own arithmetic give 55 total (-19%). Minor doc fix needed. No other issues found. |
PAGE-C1 and PAGE-C2 were two separate IS_BYTE[init, 0] and IS_BYTE[fini, 0] interactions. Since INIT and FINI are in the same row, batch them as a single IS_BYTE[init, fini] interaction. The BITWISE table's (X, Y) lookup ensures both bytes are individually constrained to [0, 255]. Saves 1 bus interaction per PAGE row (4096 rows per page). For a program touching 20 pages, this eliminates 20 * 4096 = 81920 IS_BYTE multiplicities and removes 1 aux column per PAGE table instance.
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This PR batches CPU byte range checks by unifying the IS_BYTE lookup to verify two bytes per interaction instead of one. Adjacent byte pairs in the CPU trace (e.g., ARG1[0] with ARG1[1]) are now checked together in a single bus interaction, reducing CPU bus interactions from 68 to 56 (-18%). The BITWISE chip already holds every (x, y) byte pair as part of its table, so the new lookup reuses existing rows without widening the table